1. Field of the Invention
This invention relates generally to a single-polycrystalline logic-process-compatible integrated circuit memory. More particularly this invention relates to a single-polycrystalline silicon electrically erasable programmable floating gate memory device that comprises either PMOS or NMOS transistors.
2. Description of Related Art
In the semiconductor industry, generally, there are two important types of CMOS memories. One type is a volatile memory in which the stored data are not retained when its power supply is removed or shut down. The volatile memories include Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). The other type is a non-volatile memory (NVM) in which the stored data can normally be retained for more than 20 years even after the power supply voltage source is completely disconnected.
Today, there are many different kinds of NVM memories aimed for different applications. For example, the most popular NVM today is NAND flash with a very small cell size of about 4λ2 (λ2 being the smallest area in the design rule for a given semiconductor process) and is generally used to store huge blocks of data necessary for audio and video serial applications. The second popular NVM is NOR flash with one-transistor cell of about 10λ2 and is used to store program codes. The third type of NVM is 2-transistor floating gate tunneling oxide (FLOTOX) EEPROM with a cell size of about 80λ2. Unlike NAND and NOR Flash RAM that only allow big-block data alterability, EEPROM can achieve the largest number of program/erase (P/E) cycles. In the current design, the EEPROM is capable of 1M P/E cycles when it is operated in units of bytes for small data change applications.
There are several disadvantages for NVM. The on-chip high-voltage devices, charge-pump circuits, and complicated double-polycrystalline silicon cell structure are required for basic erase and program operations. Currently the above NVM cell devices are made of a complicated double-polycrystalline silicon high-voltage process. There are several disadvantages for the double-polycrystalline NVM cells. The required voltages for performing program and erase operations are too high for devices that are fabricated using a standard CMOS logic process. For example, the current 0.5 transistor per NAND cell structure requires +20V for Fowler-Nordheim tunneling program or erase operations. For a single transistor NOR flash cell, the channel-hot-electron program operation needs about +10V. However, the Fowler-Nordheim tunneling erase operation requires both +10V and −10V. A current two-transistor EEPROM memory cell structure requires +15V for both Fowler-Nordheim tunneling program erase. As a consequence, the program and erase operations for the above described three NVM cells require an on-chip charge-pump circuit that provides the high-voltage levels in the range from approximately 10V to approximately 20V. The peripheral devices of the NVM array thus require a high voltage breakdown for the operation. The high-voltage breakdown voltages are not compatible with the current process technology for the peripheral single-poly low-voltage logic devices. Having to implement the necessary process modifications to accomplish this high-voltage breakdown device result in increased manufacturing cost.
“A New Single-Poly Flash Memory Cell with Low-Voltage and Low-Power Operations for Embedded Applications”, Chi, et al., The 5th Annual IEEE Device Research Conference Digest, June 1997, pp: 126-127, discusses a single-poly flash memory cell structure using triple-well CMOS technology and new program/erase schemes with operating voltage not exceeding the power voltage sources +/−Vcc. Conventional single-poly EPROM, although fully compatible with standard CMOS fabrication, has the disadvantages of high-voltage operations, slow programming, and not electrically erasable. The flash cell with the program/erase schemes permits low-voltage and low-power nonvolatile memory applications in CMOS mixed-signal circuits of system-on-a-chip.
U.S. Pat. No. 5,929,478 to Parris, et al. describes a single level gate nonvolatile memory device that includes a floating gate FET and a capacitor fabricated in two P-wells formed in an N-epitaxial layer on a P-substrate. P+ sinkers and N-type buried layers provide isolation between the two P-wells. The NVM device is programmed or erased by biasing the FET and the capacitor to move charge carriers onto or away from a conductive layer which serves as a floating gate of the FET. Data are read from the NVM device by sensing a current flowing in the FET while applying a reading voltage to the capacitor.
U.S. Pat. Nos. 6,992,927 and 7,164,606 to Poplevine, et al. provides a NVM array that includes four transistor PMOS non-volatile memory (NVM) cells having commonly connected floating gates. Each of the four transistors executes distinct control, erase, write and read operations, thereby allowing each device to be individually selected and optimized for performing its respective operation.
U.S. Provisional patent application Ser. No. 12/378,036, filed by the same applicant as the present invention, presented a single polycrystalline silicon floating gate nonvolatile memory cell that has a MOS capacitor and a storage MOS transistor fabricated with dimensions that can be fabricated using current low voltage logic integrated circuit process. The MOS capacitor has a first plate connected to a gate of the storage MOS transistor to form a floating gate node. Although the single polycrystalline silicon floating gate nonvolatile memory cell using a MOS capacitor can be fabricated using current low voltage logic integrated circuit process, the physical size of the MOS capacitor is relatively large in order to establish a large coupling ratio. As a result, the size of the memory cell is also large and makes it difficult to miniaturize the memory device or the integrated circuit using such single polycrystalline silicon floating gate nonvolatile memory cells.